Cadence SPB Allegro and OrCAD 17.20.000-2016 HF061

Cadence SPB Allegro and OrCAD 17.20.000-2016 HF061

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Cadence SPB Allegro and OrCAD 17.20.000-2016 HF061 | 3.9 Gb

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled a new of improvements to the Cadence SPB Allegro and OrCAD 17.20 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.


- ADW FLOW_MGR EDM Flow Manager crashes on opening TDO-enabled projects on some versions of Linux
- ALLEGRO_EDITOR DATABASE For multi-zone flex board with one and two layers, drill legend for mechanical hole not created in one-layer zone
- ALLEGRO_EDITOR DFM DFF Copper Spacing - Trace to Thru via hole false error, typically on arc segments
- ALLEGRO_EDITOR DFM DFF CF sliver violation not detected when shape formed is too narrow
- ALLEGRO_EDITOR DFM PCB Editor crashes on moving line in board file
- ALLEGRO_EDITOR DFM DesignTrue mask to trace and mask to shape checking not performing correctly
- ALLEGRO_EDITOR DFM DesignTrue DFF annular ring fiducial to antipad checks not working.
- ALLEGRO_EDITOR DFM DesignTrue annular ring SMD pin to antipad checks not working in HotFix 058
- ALLEGRO_EDITOR DFM DesignTrue DFM: plated slot annular ring pad to mask checks inconsistent
- ALLEGRO_EDITOR DFM Thieving vias are treated as antenna vias in DesignTrue DFF copper features antenna via checks
- ALLEGRO_EDITOR EDIT_ETCH When routing to an unused suppressed via padstack, PCB Editor is not following the cline to drill constraint value
- ALLEGRO_EDITOR EDIT_ETCH Crash on editing board file
- ALLEGRO_EDITOR EDIT_ETCH Unable to route with Hug or Shove selected as Bubble type and unused pad suppression enabled
- ALLEGRO_EDITOR EDIT_ETCH Incremental move using ix for sliding via slides via in y direction as well for Pre-select operation
- ALLEGRO_EDITOR INTERACTIV Using axlAirGap(),testing with a NPTH padstack which has no pad, the coordinates are swapped in return value.
- ALLEGRO_EDITOR INTERACTIV Inconsistencies while defining and adding properties to text objects
- ALLEGRO_EDITOR INTERACTIV OrCAD PCB Design crashes when modifying Outline Vertex
- ALLEGRO_EDITOR MANUFACT Silkscreen is different for rounded rectangle pads and rectangular pads
- ALLEGRO_EDITOR MANUFACT 'Clear soldermask pad' option is not working in 'Auto Silkscreen'
- ALLEGRO_EDITOR MANUFACT Autosilk bug causes WARNING(SPMHA1-36): Illegal LINE identifier - while running a symbol update
- ALLEGRO_EDITOR SHAPE Same net shape to hole spacing is only detecting DRC and not voiding shape
- ALLEGRO_EDITOR SHAPE Tapered Trace - 'Desired Angle' reset to default value (60)
- ALLEGRO_EDITOR SHAPE Tapered shape - 'Desired Angle' reset to 60
- ALLEGRO_EDITOR SHAPE Tapered trace angle does not work
- ALLEGRO_EDITOR SHAPE Taper trace does not keep the desired angle when form is closed
- ALLEGRO_PROD_TOOLB CORE Panelization with the Productivity Toolbox is deleting design outline
- ALLEGRO_PROD_TOOLB CORE PCB design compare cannot compare Cross-section layer name with space
- APD SHAPE Dynamic shape not voiding consistently
- CONCEPT_HDL CORE Wire > NetGroup > Edit. crashes DE-HDL
- CONCEPT_HDL CORE DE-HDL crashes on saving hierarchy for large designs
- CONSTRAINT_MGR SCM Clicking Resolve in the 'Alias Property Conflict Report' does not perform any action
- CONSTRAINT_MGR UI_FORMS Enabling Directly-Set filter in Physical or Spacing CSet worksheet crashes PCB Editor
- PSPICE AA_FLOW Distribution defined in DIST property on part is not honored
- PSPICE AA_MC PSpice AA MC log file is not showing error if distribution is not defined
- PSPICE AA_MC Distribution cannot be defined at the global level in assign tolerance GUI
- PSPICE AA_MC PSpice Advanced Analysis MC - distribution in global tolerance window does not work
- SIP_LAYOUT DATABASE Results are not consistent on turning on/off the pins/vias in the Color Dialog box using the Visibility tab
Cadence Design Systems announced new capabilities for OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.

This OrCAD portfolio includes new advanced technology enabled for integrated rigid-flex planning, design and real-time visualization, as well as built-in translators that enable direct design imports from select EDA vendors. PSpice Designer now supports system-level simulation using C/C++/SystemC and VerilogA, via the new PSpice compact model interface. This enables hardware/software virtual prototyping so that electrical engineers can design and simulate intelligent IoT devices. OrCAD is the only fully scalable PCB design solution available in the market that seamlessly transitions from mainstream to enterprise PCB solution with the Allegro environment.

To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD portfolio uses a new multi-stack-up database capability and extensive in-design inter-layer checks, which helps users avoid errors introduced through manual checking. The OrCAD portfolio also features enhancements targeted towards improving PCB editors' productivity and ease-of-use in padstack editing, constraint management, shape editing and in-design DRCs. To address efficiency needs, the portfolio includes an advanced design differencing engine that enables design review with global teams using state of art visuals. Finally, to give designers more control over their design component annotation process, advanced annotation and auto-referencing capabilities are now available.

Allegro 17.2 release introduces many new capabilities for Flex and Rigid-Flex designs.


Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Product: Cadence SPB Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF061
Supported Architectures: x64
Website Home Page :
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Language: english
System Requirements: PC *
Supported Operating Systems: *
Software Prerequisites: Cadence SPB Allegro and OrCAD 17.20.000-2016 and above
Size: 3.9 Gb

Cadence Allegro and OrCAD 17.2-2016 Hardware and Software Requirements:

Operating System:
Microsoft Windows 7 Professional, Enterprise, Ultimate or Home Premium (64-bit); Windows 8 (64-bit) (All Service Packs); Windows 10 (64-bit); Windows 2008 R2 Server; Windows 2012 Server (All Service Packs).
Note:Cadence Allegro and OrCAD (Including EDM) products do not support Windows 7 Starter and Home Basic. In addition, Windows Server support does not include support for Windows Remote Desktop. Windows RT and Tablets are not supported.
Minimum Hardware:
- Intel Pentium 4 or AMD Athlon XP 2000 with multi-core CPU
- Ram:8 GB RAM
- Virtual memory at least twice physical memory
- 50 GB free disk space
- 1,024 x 768 display resolution with true color (16-bit color)
- Broadband Internet connection for some service
- Ethernet card (for network communications and security hostID)
- Three-button Microsoft-compatible mouse
Recommended Hardware:
- Intel Core 2 Duo 2.66 GHz or AMD Athlon 64 X2 5200+
- Note: Faster processors are preferred.
- RAM:8 GB RAM
- Disk:500 GB free disk space
- Display:1,280 x 1024 display resolution with true color (at least 32bit color)
- GPU:A dedicated graphics card
- Display:Dual monitors
- Microsoft Internet Explorer 11.0 or later

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